System architectures with shared memory structures are well known in the art. A shared or global memory space may be accessed by multiple processors or processing elements through a bus or interconnect system. The processing elements are notionally referred to as “bus masters” of the interconnect system, and the shared memory structure resides at the “slave” end. The bus masters make read/write requests to the shared memory resource. The requests are serviced by “memory controllers” at the slave end. In general, the memory controllers complete a point to point connection between a bus master and the common memory space in the interconnect system, in order to facilitate the transfer of data.
In order to increase the memory access speed, the shared memory space is typically interleaved. An interleaved memory system comprises two or more memory channels. A memory channel generally refers to a pathway between a computer system and peripheral devices. Memory data is distributed among the memory channels such that data words in different memory channels may be accessed in parallel.
It is quite common for multiple bus masters to compete with one another for accessing the shared memory space, since only one access request may be serviceable by a memory controller at any given time. Therefore, access of the shared memory is synchronized such that a bus master is not granted access, while another bus master is being serviced. Scheduling mechanisms or “arbitration schemes” are employed to synchronize and schedule requests from different bus masters in order to avoid contentions. A “bus arbiter” performs the task of arbitration.
A bus arbiter decides which bus master may be granted access to the memory at any given time. When two or more bus masters direct requests to a particular memory controller concurrently, only one is granted access, while the other masters must wait. One of the challenges faced by arbiters is ensuring that prioritizing certain bus masters to enable them to access the memory does not cause bus masters with lower priority to get locked out indefinitely or suffer unreasonable delays in gaining access. The maximum delay that can be incurred by a bus master, while ensuring error-free system behavior is generally referred to as the “latency characteristic” or “latency requirement” of the bus master.
A common arbitration scheme is a round robin arbitration scheme, wherein the available bandwidth is allocated evenly among all the bus masters. Memory access is granted according to a predetermined order without regard to latency requirements of individual bus masters. For example, a Digital Signal Processor (DSP) processing voice communications may require low latency communications, but a basic round robin scheme may prove to be very inefficient in accommodating such latency characteristics.
Another well known approach is a token based approach wherein a “token” is passed around the network and only a bus master possessing the token may be allowed access. Notions of priority and latency requirements are built into implementations of such schemes. A token based arbitration scheme attempts to guarantee latency requirements by allocating priority based on latency characteristics of the bus masters.
However, these and other well known arbitration schemes only consider latency requirements of bus masters in the arbitration process, and do not take into account the transactions at the slave end of the interconnect system. This often results in degradation of system performance and increased power consumption. For example, one of ordinary skill in the art will recognize that a common technique of reducing power consumption is to maintain logic elements of the system that are not actively used at any given time, in a “sleep” or “powered down” mode. “Powered down” mode may be defined as logic elements maintained with less applied power or no applied power, relative to the power applied to logic elements maintained in active states. Accordingly, well known techniques are employed to maintain memory channels in a powered down mode when they are not accessed. However, the process of powering down and subsequent powering up of the memory channels is itself expensive. Therefore power consumption is decreased by increasing the duration of time that a memory channel is uninterruptedly in a powered down mode, and decreasing the number of “wake up” operations.
In a conventional arbitration scheme, the bus arbiter does not differentiate between memory channels that are powered down and those that are currently being accessed (active) in deciding which bus master should be granted access. Thus, situations are commonly encountered, wherein granting access to a particular bus master would entail waking up a memory channel that was in powered down mode heretofore. However, it is also common that in a memory system, only a small subset of the bus masters have low latency requirements, wherein access requests need to be fulfilled immediately. The remaining bus masters have larger latency requirements. Therefore, a memory channel may be frequently woken up in order to service a request from a bus master which can afford to wait longer before being serviced.
By taking into account that a particular memory channel is powered down, a bus arbiter can delay servicing access requests to that memory channel from bus masters with high latency characteristics, such that the memory channel is maintained in powered down mode for the longest duration possible before the servicing must be completed. As a corollary, activity on memory channels which are already active may be maximized by prioritizing memory access requests to active memory channels over powered down memory channels. Significant power savings may be achieved by employing such arbitration schemes which take into account the “power mode” of memory channels at the slave side of the bus system. Accordingly, there is a need in the art for such techniques.